RTL (DE) domain Engineers – DE/RTL JD :
. Expertise proficiency in VHDL and Verilog
. RTL logic design experience, working at IP or SOC level.
. SoC RTL integration
. Prefer Standard IP Controller design experience like PCIe, USB, Ethernet, WLAN. MIPI, HDMI-
. Spyglass Lint/CDC/RDC experience.
. Experience in low power design principles, UPF flows.
. STA timing constraint experience
. General expertise in infrastructure, tools like perl, python etc.
. Expected time for onboarding : within next 3-6 weeks
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