Job Description
Have you taken a career break and are now interested in returning to the workforce Intel is offering a 20-week paid returnship for experienced professionals ready to return to the workforce. If you have at least 3 years of professional experience and have taken a career break for 2+ years for any of the following, but not limited to reasons we welcome, you to apply: Starting or raising a family Military service/military spouse Community service/volunteer work Caring for a family member or self Teaching Other At Intel we are excited to have a Return-to-Work program because we appreciate the skills individuals who are returning to work can offer. Through this program you will have the opportunity to revamp your skills, update your resume with new skills and experiences as well as make connections with others transitioning back into the workforce. This position is hybrid in Bangalore during the 20-week returnship program. Intel IPG CICG team is providing exciting design solutions to different SoC’s in all latest and greatest technologies and process nodes. As the Analog Layout Designer you will be responsible for but not limited to working on these challenging designs and technologies. Additionally, you will handle Larger Layout blocks independently ( RX, TX, LDOs ), must be able to create an execution plan, estimate efforts for the blocks and lead a small team of layout designers, assign and track work. You will work with leads on top level layout, and provide inputs for efficient floorplans. Expectation will be that the person will work as an individual contributor, with an added responsibility to technically lead a small team of Layout designers to complete layout of larger designs.
Qualifications
You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. This position is not eligible for Intel immigration sponsorship. Minimum Qualifications Candidates must have taken a career break for 2 or more years. Candidates must have a minimum of 3 Years of professional experience in Analog Layout Design Bachelors in Electronics Preferred Qualifications A good understanding of RV, ESD and Analog layout skills Expert in all flows and tools like Genesys/Virtuoso, Hercules/ICV, Redhawk, Extraction tools and Knowledgeable of Rule Decks. Understanding of complex ckt ADC, vregs, DACs, current mirrors, PLLs, Chargepumps, and amplifiersInside this Business Group
IP Engineering Group’s (IPG) vision Build IPs that power Intel’s leadership products and power our customer’s silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel’s silicon design process. IPG’s guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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