Job Description
Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLT is part of the Chipsets Silicon Group, CSG within Design Engineering Group, DEG and is responsible for developing soft IPs and subsystems for client and server chipsets. Candidate will be responsible for logic design and development, responsibilities including but not limited to: – Participates in the development of Architecture and Microarchitecture specifications for the Logic components – Creates Detailed designs, Performs logic design, Register Transfer Level RTL coding, for creating IPs which will be included in full chip or SoC designs – Applies various strategies, tools and methods to qualify the design for lint, synthesizability, DFx, clock and reset domain crossing check, synthesizability check to meet design QoR, timing constraint definition and review gate count, power optimization, etc – Reviewing verification plan and implementation to ensure the design features are verified correctly – Provides IP integration support to SoC customers and represents RTL team. Excellent communication and organization skills are critical, along with teamwork, and must demonstrate strong technical leadership skills, passion for design, tools and methodology and strong influencing skills. Candidate must have strong orientation for Quality, Commit and Deliver, drive Innovation and efficiencies, and have strong strategic thinking to come up with paradigm shift solutions to critical design and validation challenges.
Qualifications
The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate must have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Other technical requirements: – 10+ years of relevant logic design, microarchitecture or pre silicon verification experience with multiple project cycles. – 5+ years of PC Architecture experience. – 5+ years of experience in developing micro architect specifications based on High Level Architecture specifications. – experienced in VLSI or Structural and Physical design flow and methodology, SIP and HIP interoperability. – experienced in Power-aware design and validation flows. – Strong analysis debugging skills and creative in problem solving. – experienced with various tools and methodologies including but not limited to: o System Verilog for design, o Python, Perl, Shell scripting, o logic simulators and debuggers from major EDAs, o RTL model build and testbench development flow, o design for test, design for verification, o structural design flows, performance verification, scan coverage. o coverage based random constraint simulation. Candidate will have advantage if experienced in any below: – experienced in UFS, SATA, AMBA, PCI express or any industry standard BUS protocol. – strong chipset or CPU level understanding on power consumption, power estimation and low power design methods. – capable in reviewing test plans , and add coverage points for validation purpose based on High Level Architecture specifications.Inside this Business Group
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
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